1. Field of the Invention
This invention relates to a speed-up technique for realizing a quick processing in response to a branch instruction or in an exceptional treatment or handling based on an internal vector.
2. Related Art
In general, instruction address operations in a micro processor are classified into two categories, i.e. fixed command operations in accordance with ordinary instructions and non-fixed command operations in accordance with branch instructions or the like.
In the case of ordinary instructions, their instruction addresses are calculated during an IF (instruction fetch) stage. On the other hand, in the case of branch instructions, their instruction addresses are calculated during an EX (execution of operation) stage. Branch instructions generally comprise the addressing mode such as a program counter relative branch, an immediate branch, and a register direct branch. Among them, the program counter relative branch is an instruction to execute the operation of the program counter and a relative value at the EX stage. On the other hand, the immediate branch and the register direct branch are instructions both dealing with their branch addresses as immediate values, and hence they execute the processing for setting immediate value to the program counter in the EX stage (Refer to "H8/327, SH7032 Programming Manuals of Hitachi, or RISC System by K. Ohmori, Kaibundo publishing Co., Ltd.).
As one of this kind of conventional technologies, a micro processor adopting a 5-stage pipeline processing system will be explained hereinafter.
Sequential five stages of this pipeline processing consists of IF (instruction fetch), ID (instruction decode), EX (execution of operation), MA (memory access) and WB (write back) stages. FIG. 5 shows the sequential flow representing the ordinary 5-stage pipeline processing.
FIG. 6 shows the arrangement of a conventional micro processor which comprises a decoder 1 and a data path 2. Data path 2 comprises an operating section 2-1 performing logical operations, arithmetic operations, shift operations and so on, a register file 2-2 storing the operation or computation data, a program counter 2-3 counting the address of the present program, and an address unit 2-4 selectively switching the output to an address bus 4 from operating section 2-1 or program counter 2-3. Operating section 2-1 through address unit 2-4 are respectively controlled in response to the signals of control buses 7-1 through 7-4 fed from decoder 1.
Micro processor designates an address in a memory (not shown) by outputting data through address bus 4 and reads out the instruction stored in the designated address through data bus 3, and then decodes the readout instruction in decoder 1, thereby controlling the data path 2.
An immediate bus 6-1 is provided between decoder 1 and operating section 2-1. Read buses 6-2 and 6-4 are provided to read out the data from register file 2-2. Reference numerals 6-3 and 6-5 represent input buses of operating section 2-1, while 6-6 represents an output bus of operating section 2-1. Furthermore, reference numeral 6-7 represents a read bus of program counter 2-3, and 6-8 represents an input bus of address unit 2-4. There are also provided a plurality of bidirectional switches 5-1 through 5-6 to switch the above-described buses 6-1, 6-2, 6-4, 6-5, 6-6 and 6-7.
Regarding operation timing, each stage of IF through WB has the following relationship or correspondence to each of units 2-1 through 2-4 constituting the data path 2.
Program counter 2-3 operates during the IF stage. Decoder 1 (control section) and register file 2-2 operate during the ID stage. Operating section 2-1 operates during the EX stage. Address unit 2-4 operates during the MA stage. And, register file 2-2 operates during the WB stage.
The immediate branch instruction in the above-described conventional micro processor is executed according to the pipeline flow shown in FIG. 7. More specifically, the branch address decoded in decoder 1 is entered from immediate bus 6-1 to operating section 2-1 in EX stage 301 and then is set through output bus 6-6 to program counter 2-3.
Similarly, in executing the register direct branch instruction in the above-described micro processor, the branch address is read out from register file 2-2 and is entered through buses 6-4 and 6-5 to operating section 2-1, and is then set via bus 6-6 to program counter 2-3.
In this manner, according to the above-described conventional micro processor, the branch address is always set to the program counter 2-3 via operating section 2-1 in the response to the branch instruction or in the exceptional treatment. Hence, when seen on the processing stage flow, the above-described micro processor is forced to pass through the EX stage every time, resulting in a significant delay in the processing speed.
Furthermore, FIG. 11 shows the relationship between the instruction processing cycle and each stage in a micro processor adopting the 5-stage pipeline processing system.
In this example, it is now assumed that a conditional branch instruction is fetched inn instruction processing cycle. This conditional branch instruction is decoded in the ID stage. There is a waiting time for waiting the operation result coming from the EX stage of the immediately preceding n-1 instruction processing cycle. Then, at the timing of ID stage of the own n instruction processing cycle, the operation result obtained from the n-1 instruction processing cycle is compared with the branch condition. Thereafter, the processing flow proceeds to the EX stage of the branch address.
For this reason, the ID stage of the n instruction processing cycle requires a relatively long time L equivalent to the sum of a first duration required for waiting the operation result obtained from the n-1 instruction processing cycle and a second duration required for comparing the operation result thus obtained and the condition of the branch instruction. In other words, according to the above-described conventional pipeline processing, the length of a particular stage, if it has the longest time, will make other stages delay in their processing time.